Shallow trench isolation (STI) technology is generally used to insulate adjacent NMOS and PMOS transistors in manufacturing of Complementary Metal-Oxide Semiconductor (CMOS) devices.
As described in U.S. Pat. No. 7,436,030, with the continuous scaling of the dimension of semiconductor devices, STI technology has become the preferable method for electrical isolation of CMOS devices. This is because STI stress may induce strain of the channel, which may enhance the whole performance of the semiconductor device. However, it is known for those skilled in the art that, for a CMOS device, while STI stress may enhance performance of one type of MOS transistor, e.g. NMOS transistor, it may degrade performance of another type of MOS transistor, e.g. PMOS transistor. For instance, STI tensile stress may improve the driving current of an NMOS transistor by increasing electrons mobility, while decreasing mobility of holes so that the driving current of the neighboring PMOS transistor may be decreased. Therefore, a new STI process is needed to solve the problems caused by the conventional STI process, so as to sufficiently employ the stress provided by the STI in MOS transistors.